1. Field of the Invention
The present invention generally relates to memory devices, and more particularly, the present invention relates to phase change memory cell arrays.
A claim of priority is made to Korean Patent Application No. 2003-12812, filed on Feb. 28, 2003, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Phase change memory cell devices rely on phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The differing resistance values exhibited by the two phases are used to distinguish logic values of the memory cells. That is, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.
The phase of the phase change material of each memory cell is set by Joule heating of the material according to an amount of current passed through the material. To obtain an amorphous state (referred to as a “reset” state), a relatively high current is passed through the phase change material to melt the material for a short period of time. The current is removed and the cell cools rapidly to below the melting point. The melting point of chalcogenide, for example, is approximately 610° C. To obtain a crystalline state (referred to as a “set” state), a lower current pulse is applied to the material for a longer period of time. This causes the material to re-crystallize to a crystalline state which is maintained once the current is removed and the cell is rapidly cooled. For example, in the case of a chalcogenide material, current is applied to obtain a crystallization temperature of approximately 210° C. for a few tens of nanoseconds.
FIG. 1 is a circuit representation of a conventional phase change memory. As shown, the phase change memory 100 includes an array of phase change memory cells, each of which includes a cell transistor CTR, a phase change cell PCC, and a resistor R. The cell transistor CTR has a gate connected to a word line WL. The phase change cell PCC is serially connected to the resistor R between a drain of the cell transistor CTR and a bit line BL. When both the word line WL and the bit line BL of a corresponding memory cell are selected, a current is applied to the phase change cell PCC of the memory cell to switch the state of the phase change cell PCC.
As mentioned above, the phase change cell PCC relies on Joule heating to change its state, and a relatively high write current is needed to obtain the required level of heating. Hence, the cell transistor of each memory cell must have a current drive capacity which is superior to that of other memory devices.
Unfortunately, it is difficult to satisfactorily achieve the necessary cell current drive using conventional CMOS process technology. For example, any increase in drive current must be attended by an increase in the width of the phase change cell transistor. This increases the overall size of the phase change cell, which runs counter to industry demands towards increased integration.
In an attempt to obtain a sufficient cell drive current of the phase change memory, many studies have proposed the use of bipolar junction transistors as the cell transistors of the phase change memory. This is because the current drive capacity of the bipolar junction transistor is superior to that of the CMOS transistor. More specifically, it has recently been suggested that BiCMOS process technology be adopted in which the phase change memory is fabricated to include CMOS transistor control circuits and bipolar junction cell transistors. However, when compared to CMOS technology, BiCMOS technology is difficult to control and is characterized by highly complex design and manufacturing processes.